In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, and PMOS elements, are formed on a single chip area. Typically, feature sizes of these circuit elements are decreased with the introduction of every new circuit generation, to provide currently available integrated circuits with high performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors and resistors, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be improved, but also their packing density may be significantly increased, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SOC). Precise polysilicon resistor has been used in conventional integrated circuit (IC) design. When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, a high-k dielectric material and metal are adopted to form a gate stack. For gate replacement processes, the resistance of the formed polysilicon resistors is too low. A single crystalline silicon resistor has been proposed to resolve the issue. However, the single crystalline silicon resistor cannot provide precise impedance matching for the applications, such as analog, radio frequency (RF), and mixed-mode circuits.
For example, in sophisticated applications, resistors may frequently be provided in the form of “integrated polysilicon” resistors, which may be formed above isolation structures so as to obtain the desired resistance value without significantly contributing to parasitic capacitance, as may be the case in “buried” resistive structures which may be formed within the active semiconductor layer. A typical polysilicon resistor may thus require the deposition of the basic polysilicon material, which may frequently be combined with the deposition of a polysilicon gate electrode material for the transistor elements. During the patterning of the gate electrode structures, the resistors are formed, the size of which may significantly depend on the basic specific resistance value of the polysilicon material and the type of dopant material and concentration that may be incorporated into the resistors so as to adjust the resistance values. Since typically the resistance value of doped polysilicon material may be a non-linear function of the dopant concentration, specific implantation processes are required, independent of any other implantation sequences for adjusting the characteristics of the polysilicon material of the gate electrodes of the transistors.
Transistor performance may further be increased by providing an appropriate conductive material for the gate electrode in order to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface positioned between the gate dielectric material and the polysilicon material, thereby reducing the effective capacitance between the channel region and the gate electrode during transistor operation. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance, while additionally maintaining any leakage currents at an acceptable level. Since the non-polysilicon material, such as titanium nitride, may be formed such that it may directly be in contact with gate dielectric material, the presence of a depletion zone may thus be avoided, while, at the same time, a moderately high conductivity is achieved.
As is well known, the threshold voltage of the transistor may depend on the overall transistor configuration, on a complex lateral and vertical dopant profile of the drain and source regions and the corresponding configuration of the PN junctions, and on the work function of the gate electrode material. Consequently, in addition to providing the desired dopant profiles, the work function of the metal-containing gate electrode material also has to be appropriately adjusted with respect to the conductivity type of the transistor under consideration. For this reason, typically, metal-containing electrode materials may be used for N-channel transistors and P-channel transistors, which may be provided according to well-established manufacturing strategies in a very advanced manufacturing stage.
In some of these so-called replacement gate approaches, the high-k dielectric material may be formed in combination with a titanium nitride cap material, which may thus be used as an efficient material for confining the sensitive high-k material and providing a moderately high conductive material layer in close proximity to the gate dielectric material. Thereafter, silicon in an amorphous state is provided so as to act as a placeholder material since the amorphous silicon material may be replaced in a very advanced manufacturing stage. The resulting layer stack in combination with any additional sacrificial materials, such as dielectric cap materials and the like, may then be patterned into a gate electrode structure. Concurrently, the corresponding resistors are formed as described above. Subsequently, any further processes are performed in order to complete the basic transistor configuration by forming drain and source regions, performing anneal processes and finally embedding the transistors and also the resistors in a dielectric material. Consequently, after any high temperature anneal processes, an appropriate material removal sequence may be applied in order to expose the placeholder silicon material, which may then be removed in the gate electrode structures on the basis of highly selective etch processes. Based on an appropriate masking regime, thereafter, appropriate metal-containing electrode materials are filled into the gate electrode structures of N-channel transistors and P-channel transistors in order to adjust the required work function for these different types of transistors. Moreover, a highly conductive electrode metal, such as aluminum and the like, may be filled into the gate electrode structures. In this manner, superior gate conductivity and the desired high degree of channel controllability may be achieved. Furthermore, the work function may be adjusted, for instance, by providing appropriate metal species, wherein any drift in transistor characteristics may be substantially eliminated since any high temperature processes have been performed in the earlier manufacturing phase. In this patterning regime, the resistive structures may also receive the electrode metal, thereby imparting superior conductivity to the resistive structures, which, however, may thus reduce the resistance value, thereby requiring a reduction in line width of the resistors and/or an increase of the total length of the resistors. While the former measure may result in patterning problems since extremely small line widths have to be provided, the latter aspect may result in increased area consumption in the semiconductor die.
For these reasons, it has been proposed to remove the amorphous silicon material selectively from the gate electrode structures and preserving the silicon material in the resistors by appropriate masking regimes and the like. Although the resistance value may be significantly reduced upon preserving the amorphous silicon material, it has nevertheless been recognized that the resulting resistivity may still require significant redesigns of silicon-based resistors when formed in accordance with the above-described replacement gate approaches.
Another way of compensating for the higher resistance polysilicon materials is to replace a polysilicon gate device with a metal gate device. This replacement can be done with a replacement metal gate (RMG) process, wherein the higher temperature processing is performed while the polysilicon is present in the substrate, and after such processing, the polysilicon is removed and replaced with metal to form the replacement metal gate. More specifically, a device with a disposable polysilicon gate is processed, and the disposable gate and dielectrics are etched away, exposing an original gate oxide. The disposable polysilicon gate is then replaced by a metal gate having lower resistivity than the polysilicon material.
In known RMG processes, polysilicon is also removed from the areas forming resistors on the substrate, and replaced with metallic materials. As a result, the high resistive properties of polysilicon are not utilized for resistors on a substrate in which RMG processing has been performed.
Accordingly, it would be desirable to provide an RMG semiconductor fabrication process that is compatible with polysilicon resistor structures. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.